(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit able to switch the operational mode of an internal circuit. More particularly, it relates to a semiconductor integrated circuit comprising a memory cell array which can be switched from a usual mode to a test mode, or vice versa, in accordance with the potential value of an input signal supplied from an external input terminal.
(2) Description of the Related Art
Recently, the capacity of a memory cell array has been increased and when a memory cell array having a large capacity (e.g., 1 (mega words).times.1 (bit)) is tested, the time needed for successively writing test data to each of the memory cells, and for successively reading test data from each of the memory cells, is increased. For example, if a test of a dynamic RAM having the above capacity and a cycle time of about 260 nano seconds is carried out using a March pattern (a well known test pattern), a test time of about 3.2 seconds is needed for carrying out the above test. Also, the test time is further increased according to the increase of the kinds of tests needed, and accordingly, the cost of carrying out these tests is also increased.
Thus, in order to test a memory cell array having a large capacity within a comparatively short time, the memory cell array is divided into several memory blocks, and each memory block is connected to a data input terminal and a data output terminal through a functional block for usual operation, which functions when the memory cell array operates in a usual mode, and a functional block for testing which functions when the memory cell array operates in a test mode. The functional block for a usual operation usually comprises a decoder for selecting one of the memory blocks.
Thus, in a write mode, predetermined write data is written to a predetermined memory cell arranged in the memory block selected by the decoder provided in the functional block for a usual operation. On the other hand, in a read mode, data written in a predetermined memory cell arranged in the memory block selected by the above decoder is output as read data.
Further, when a test for the memory cell array is carried out, the above circuits formed through the functional block for a usual operation are switched to the circuits formed through the functional block for testing, and the test data is simultaneously written to each of the corresponding memory cells arranged in each of the memory blocks, through the functional block for testing. Thus, in a test mode, it is possible to simultaneously carry out a test for all memory blocks within a relatively short time.
In the semiconductor integrated circuit having a construction such as above, it is necessary to provide a terminal for supplying a signal for switching the operational mode of the memory cell array from the outside, e.g., for switching the memory cell array from a usual mode to a test mode, or vice versa.
However, the number of terminals which can be provided in the package receiving the chip of the semiconductor integrated circuit is limited, and therefore, it is difficult to provide an exclusive terminal in the package for receiving the signal for switching the operational mode of the memory cell array from the outside and thus carry out the test for the memory cell array after the chip has been received in the package, especially when the capacity of the memory cell array has been increased.
Accordingly, it has been proposed to supply an input signal from the outside, this input signal having a potential set to a different value in the test mode from that of the input signal supplied in a usual mode, by using an existing terminal provided in the package (e.g., an address terminal connected to the above decoder for selecting one of the memory blocks), and to switch the operational mode of the memory cell array from a usual mode to a test mode, or vice versa, in accordance with a signal output by a voltage detecting circuit which detects the potential of the input signal.
However, in the conventional voltage detecting circuit, if the input signal having a predetermined potential is supplied from the outside to an external input terminal (e.g., the address terminal connected to the above decoder), a predetermined leak current flows into the external input terminal even when the operational mode of the internal circuit is in the usual mode.
In this connection, in such a semiconductor integrated circuit, the leak current due to the input signal flowing from the outside into the external input terminal of the semiconductor integrated circuit is limited to within, for example, 10 .mu.A (microamperes), as a rated value.
Such a rated value is usually determined in accordance with a driving ability of the driver circuit for the semiconductor integrated circuit comprising, for example, the dynamic RAM. Namely, considering the actual state in the usual mode of such a semiconductor integrated circuit, a number of semiconductor integrated circuits (about one hundred semiconductor integrated circuits, for example) are often driven in parallel by a common driver circuit.
Therefore, if one hundred semiconductor integrated circuits are driven by the common driver circuit and the value of each leak current flowing from the driver circuit into each external input terminal of the semiconductor integrated circuits exceeds the above rated value (i.e., 10 .mu.A), the driver circuit must output a current having a total value in the mA (milliampere) range, in order to drive the above one hundred semiconductor integrated circuits.
Therefore, if the leak current flowing from the drive circuit into the external input terminal of the semiconductor integrated circuit exceeds the above rated value (e.g., 10 .mu.A), a problem arises in that the driving ability of the driver circuit is not sufficient for driving all of the above semiconductor integrated circuits in the usual mode and the possibility of the destruction of transistors provided in, for example, the driver circuit, may arise.